Seas C18EN001 coax in open baffle?

[5th element]

In the BeagleBone design, the on-board oscillator for audio (that I will disable and feed externally) feeds AHCLKX (not the expected AHCLKR, thus AHCLKX receives the clock), which may be explained by the AM335x Sitara Processors Technical Reference Manual (Rev. L) on page 4556 :Z

When I look at the interface used in CircuitCo:Audio Cape RevB it corresponds with the above when transmitter and receiver is configured to operate synchronously (refer the BeagleBone Black schematic). It does not use (A)FSR nor ACLKR pins.

What I'm trying to determine is if I should tie (A)FSX/(A)FSR together and ACLKX/ACLKR together in order to have bidirectional sync/clock signals, or if I should simply operate the transmitter and receiver of the McASP synchronously without (A)FSR or ACLKR signals.

Now to wrap my head around what synchronous operation means to me, the MCLK oscillator will feed the AHCLKX, and it will generate ACLKX and (A)FSX output signals. On one data line, I should be able to playback music from the BeagleBone, but for the mic input on the other data line going the other way (DSP->BeagleBone), would I resample the mic input on the DSP? (sample rate and sync will have to match the data going the other way) And would I feed the ADAU144x the (external) BeagleBone MCLK oscillator at all or would I operate it independantly from its own clock?

Okay, so when running the input and output sections synchronously you feed a master clock into the BeagleBone at one pin. This is then used as a reference and via clock division a bit clock and LR clock are generated internally. When using the BB as a datastreamer it will receiver data from whatever its source is and then clock the data out to these generated clocks. In other words if you were to use the BB to drive a DAC chip directly you would feed the externally provided master clock into both the BB and the DAC chip, you would then feed AFSX and ACLKX from the BB into the DACs corresponding pins and then hook up AXR0 as a data transmit to the data input of the DAC.

When configured as such the receiver module on the BB will be expecting to receive data clocked synchronously to those very same clocks. If you were to add in an ADC then you would simply connect AFSX and ACLKX up to the relevant pins on the ADC, along with the externally provided master clock, configure the ADC as a slave and then hook up the ADCs data output into AXR2 configured as an input.

As you mention though you do need to know if the BB will require you to physically connect the input and output bit and LR clocks together at the pins, or whether it is routed internally for you. On the SigmaDSP chips you have to route it manually yourself as the clock domains cannot be joined up physically.

Obviously I would have to set it up for synchronous operation since I have only one McASP and bidirectional data. So no (A)FSR or ACLKR. Just master clock oscillator to AHCLKX/MCLK, and let the McASP feed the DSP FSX/LRCLK and ACLKX/BCLK along with data. I guess what I'm really trying to ask is how to set this up clockwize (hah) with the DSP feeding data back in sync, with regards to resampling, etc.

I don't know why you are going to want to feed data back, or why you eve need to connect a microphone up to this. Realistically speaking the only thing you need the microphone for is for the initial measurements of the system with a suitable program such as ARTA.

If the BB is going to act as a datastreamer itself then it's fairly simple as far as I see it.

You feed the master clock into the BB to act as the high quality source. The BB then uses clock division to generate the necessary clocks which it uses to clock the streamed data out of one of its data ports. You then connect the LR clock, bit clock and data out, that the BB generates, to the input clock domain of the DSP. You then physically connect the LR clock and bit clock to the output clock domain on the DSP and configure both the input and output domains on the DSP as a slave. You disable the internal ASRCs.

After this you feed the reference master clock and the LR clock and bit clock generated by the BB into the DAC chips. You then feed the data out lines from the DSP into the DACs.

Done like this everything will be entirely synchronous to the high quality clocks and clocked data stream from the BB and should be bit perfect and low jitter. This does not require the use of any ASRCs either and is essentially how I would want everything to be configured.

Configured like that you will have to ensure that the sample rate is kept constant on the output of the BB or have the BB detect the outgoing sample rate and update the DSPs filter coefficients based on what sample rate is being used.

Obviously if you are going to be providing a master clock that operates at multiples of 48/96 and 192 kHz then you will require resampling somewhere in software to get 44.1k stuff into something appropriate first.

[Kjetil]

Lets for now assume I'd only play 48kHz family sample rates from the BB (I'll address that later with an oscillator select signal)

Oh, and lets drop the problem of feeding data to the BB, consider it a source only as you suggest.

I drew up the setup you explained on a sheet of paper, interface BB->DSP seems clear now.

On the SigmaDSP chips you have to route it manually yourself as the clock domains cannot be joined up physically.

But I can assign the other output data lines as members of the output clock domain that inputs BCLK and LRCLK right? No need to route the clocks to other output domains?

Another thing, when not playing from BB but from an SPDIF source, that input domain is slaved to SPDIF... In this case, would I want to use the ASRCs, and run the DSP off the MCLK clock and have output domains in master mode?

[Kjetil]

But I can assign the other output data lines as members of the output clock domain that inputs BCLK and LRCLK right? No need to route the clocks to other output domains?

I should have read the DS before asking that.

Although a clock domain in slave mode can clock an arbitrary number of serial ports, a clock domain in master mode can only clock a single serial port.

[Kjetil]

A work in progress... :conveyer:

[Kjetil]

Reason for having optic SPDIF out is because it seemed I had the right space in the right place, and it could be handy to test DSP output without I2S expansion available. I'll try to retain flexibility, because this board could have many uses not necessarily just audio DAC, although the clock design of course will reflect its intended purpose. I did real overkill on number of I2S input lines, but think for instance sound locators based on 4 mics using phase mismatch and simple geometry, I saw that used once on an RWS (mil computerized gunhat for light vehicles) that recognized the sound of gunfire with an alert on screen, and could automatically tune in the sight on the shooter :k>
The TIMER5 pad is for IR remote, BB expansion covers GPIOS/I2Cs/SPI/etc, also an UART in there for serial enabled LCD displays (if in need of a chassis front display). The extra EEPROM is for BeagleBone ID. I put all audio connectors at the side BeagleBone has connectors for HDMI, USB host, and microSD card, so that's the side facing the back of the chassis, hence IR (will be expansion off-board) on the opposite side...
Clock and supply is not drawn yet, but supply (3.3V reg) will be bottom right corner with option to power from baseboard.

[5th element]

Another thing, when not playing from BB but from an SPDIF source, that input domain is slaved to SPDIF... In this case, would I want to use the ASRCs, and run the DSP off the MCLK clock and have output domains in master mode?

I think it's worthwhile running the DSP from the MCLK anyway as this will keep all of the clocks synchronous so it will give you options. I am not entirely sure if the DSP chip itself uses clock division from the MCLK to generate the bit clock and LR clock when run in master mode, or whether or not it uses some sort of PLL. I would expect it to use division from the MCLK, but you never know.

There are several ways you can do this though and it entirely depends on what you are the most comfortable with.

What you need are the input and output clock domains to be slaved to the same clocks. If you are already going to have the bit clock and LR clock from the BB hard wired to an input and output clock domain of the DSP then this might limit your options. If you want to use the internal S/PDIF converter, then what I would do is have the output and input domains slaved to the clocks from the BB, but I would feed the data from the S/PDIF converter through an ASRC on the input side, before it feeds into the DSP core. This keeps everything really simple and allows the hardware to run in exactly the same configuration regardless of what the input is. This would be the simplest option from all points of view.

You could start adding in external S/PDIF converters and ASRCs and having the external ASRC slaved to the master clock too. You'd feed the S/PDIF converter into the ASRC and then with the output of the ASRC you could do whatever you wanted. It should be synchronous to the rest of the system, you could feed it into the BB if you wanted to first, for whatever reason, then feed it into the DSP, or feed it directly into the DSP.

A work in progress... :conveyer:
[ATTACH=CONFIG]24501[/ATTACH]

It looks, unsurprisingly, similar to my board

Reason for having optic SPDIF out is because it seemed I had the right space in the right place, and it could be handy to test DSP output without I2S expansion available.

This is a good idea you don't want to be messing about with I2S DACs and the DSP at the same time. I already had DACs in place so that wasn't an issue for me.

I'll try to retain flexibility, because this board could have many uses not necessarily just audio DAC, although the clock design of course will reflect its intended purpose. I did real overkill on number of I2S input lines, but think for instance sound locators based on 4 mics using phase mismatch and simple geometry, I saw that used once on an RWS (mil computerized gunhat for light vehicles) that recognized the sound of gunfire with an alert on screen, and could automatically tune in the sight on the shooter :k>
The TIMER5 pad is for IR remote, BB expansion covers GPIOS/I2Cs/SPI/etc, also an UART in there for serial enabled LCD displays (if in need of a chassis front display). The extra EEPROM is for BeagleBone ID. I put all audio connectors at the side BeagleBone has connectors for HDMI, USB host, and microSD card, so that's the side facing the back of the chassis, hence IR (will be expansion off-board) on the opposite side...
Clock and supply is not drawn yet, but supply (3.3V reg) will be bottom right corner with option to power from baseboard.

I'm running an OLED 256x64 display with my DSP and also IR. I am using a microchip micro controller for mine though, one of the PIC24E line. It's overkill actually for the application but I thought why not!

[Kjetil]

I think it's worthwhile running the DSP from the MCLK anyway as this will keep all of the clocks synchronous so it will give you options.

Agreed. No reason not to.

What you need are the input and output clock domains to be slaved to the same clocks. If you are already going to have the bit clock and LR clock from the BB hard wired to an input and output clock domain of the DSP then this might limit your options.

It would appear this is the route I'm following, yes...

If you want to use the internal S/PDIF converter, then what I would do is have the output and input domains slaved to the clocks from the BB, but I would feed the data from the S/PDIF converter through an ASRC on the input side, before it feeds into the DSP core. This keeps everything really simple and allows the hardware to run in exactly the same configuration regardless of what the input is. This would be the simplest option from all points of view.

Sounds like a very nice option, so it is settled. :agree::yesnod:

You could start adding in external S/PDIF converters

This increases circuit complexity, are there gains in performance?

It looks, unsurprisingly, similar to my board

That is good news, indeed :T
I'm quite happy with how things turned out in the PVDD/clock area with the PLL loop filter and stuff, there was so crowded at first, but I think it turned out pretty well, took a look at the layout guidelines for the faster 1452, it had some good tips (bottom of DS) but goes all berserk with 10nF+100nF decoupling. I used 0402 100nF on mine. Board is of course 4 layer, GND/POWER planes.

I'm running an OLED 256x64 display with my DSP and also IR. I am using a microchip micro controller for mine though, one of the PIC24E line. It's overkill actually for the application but I thought why not!

When laying out circuits that will not be *mass* produced and there is significant software development on the PIC I always choose a PIC24, albeit not the E version. Reason is code development is much faster than the more primitive PICs. But still between members of same PIC24 family, Microchip manages to move registers around... I wrote code once for a PIC24 in 3V variant, the same code was incompatible with the 5V variant from the same chip due to registers with different names (Don't remember the chip name, but there is not many 5V PIC24, same part codes except the last letters designating 3V/5V version)... This is why I turned to ARM Cortex, eg STM32.


As a coplete sidenote, I wonder if the SigmaDSP has the features needed to realize a Doppler Velocity Log with this board, using 2x stereo DAC out and 2x stereo ADC in...:ball:

[Kjetil]

I've rearranged a bit, put the SPDIF coax to U.FL (to save space) and think I have a nice spot for two crystal oscillators with a TI little logic SOT-23 hex inverter between enable signals, plus a dedicated SOTA LDO for the oscillators. I've kept all components except coax/optic connectors on the top side for easy reflow mount, but the oscillators (pretty expensive buggers, 20EUR/each in low qty) leaked to the bottom side for manual mount. Not too many quality oscillators at audio frequencies for some reason, but I found CCHD-957-24.576MHz and CCHD-957-22.5792MHz from Crystek. Any experiences with Crystek XOs?

EDIT: Note to self: Converting Oscillator Phase Noise to Time Jitter by Walt Kester

[Kjetil]

Progress. The board is starting to get more packed; the Crystek oscillator pair have found their place, separate TI LDO regulators for oscillators and digital supply. Clock distribution is still a complete mess, absolutely where the bulk of remaining work lies, but the rest of the circuit starts to take shape. 1.8V core supply highlighted. For some reason there is still no power connection to baseboard beside the main LDO, it'll be a 2x2 pin header with dual PWR/GND.

[Kjetil]

Silicon Labs SL18860 or SL18861 3-Channel Clock Distribution Buffer :yesnod: It concerns me a bit that clock frequencies are so high, Crystek didn't have lower freqs.:scratchhead:

[Kjetil]

If Silicon labs or others had a low jitter combined buffer / divider combo, that would really be optimum I think. Sort of a clock manager.
EDIT: Like these perhaps

[Kjetil]

Some of them are only 1.5V out, some differential, but these are the 3.3V LVCMOS parts:
http://www.silabs.com/Support%20Docu...cs/Si53308.pdf
http://www.silabs.com/Support%20Docu...cs/Si53311.pdf :T

[Kjetil]

The land pattern drawing dimensions in the Si53311 datasheet (page 27) is an example to be followed by other IC datasheet writers. It's that easy, and you don't have to use a calculator to draw it.:thanku:

[Kjetil]

OK, I've configured the Si53311 with only one clock output on bank A; Q0 and #Q0 goes to two UFL connectors, can be used with DACs with Q0 single ended or as an LVDS pair. I also have a solder pad jumper configuration of this bank for frequency division by 1/2/4. Each bank (A/B) has own divisors and output format configuration. The other bank, B, uses all its 3 outputs in single ended 3.3V LVCMOS; one as clock for DSP, one to I2S breakout header, and one to BeagleBone MCLK.

[Kjetil]

Layout is more or less done 8) but I'll take some reflection time to look everything over properly before ordering anything. Setup ended up with the ADAU1442 (8x2 ASRC). Two low-jitter Crystek oscillators at 24.576MHz and 22.5792MHz feeding the Si53311 (gem :T). Rearranged the clock output banks of the Si53311; 2x MCLK outputs to U.FL and one to I2S header are on bank A for a common divisor (1,2, or 4, adjusted to match DAC requirements), bank B provides the DSP clock and MCLK_BeagleBone, and will probably stay hard wired for division by 2 (12.288MHz, 11.2896MHz MCLK). BeagleBone I/O pins control #DSP_RESET (pulled low), OSC_SEL (pulled to select OSC0/24.576MHz and wouldn't need OSC1 mounted at all for less expensive board), and LDO_EN (bringing both LDOs up, powering everything on this board). BeagleBone will have to bring the DSP to reset in order to change clock (OSC_SEL), upload new coefficient sets to I2C EEPROM, then pull #DSP_RESET high to bring the DSP back (self boot). BeagleBone breakout header has access to some I2C/SPI/UART/GPIO/IR features along with power/reset control, and the 6-pin UART connector (linux debug terminal) that is unaccessible with the cape on, is brought out in the open. BeagleBone I2C EEPROM for "cape ID" is included, so the cape should be recognized.

The BeagleBone has a bidirectional I2S link to the DSP

The DSP I2S header has:

• 4 I2S data input lines
• 8 I2S data output lines
• 4 universal FCLK/BCLK clock I/O pairs, one of which is physically slaved/connected to the FCLK/BCLK lines of the BeagleBone->DSP I2S interface
• 1 MCLK output (Fdiv by 1,2,4)

Also 2 clock manager MCLKs from bank A are available from U.FL coax (single ended only now, no LVDS), so 3 independantly buffered MCLKs straight from the Silabs clock manager.

I'm gonna have a small look at possibly buffering BCLK/FCLK from Beaglebone, but that's about it, not much left to do. Already began ground stitching. 8x) But I've had much time for play lately, a temporary privilegie that seems to come to an end, so things will probably move at a slower pace forward. And there will be *lots* to do on the Linux side forward. :sos:

[Kjetil]

Well, playing from SDPIF/optic to I2S with ASRCs won't be that much work I suppose, all Linux need to do is program I2C EEPROM and pull DSP_RESET high... but playing synchronously from BeagleBone at different sample rates is another matter.

[Kjetil]

Yep, I'll buffer the BCLK/FCLK from the beaglebone->DSP bus with a SN74LVC2G125 Dual Bus Buffer Gate with 3-State Outputs. That way I can 3-state the BCLK/FCLK at I2S output from being physically slaved, as to play from SPDIF->ASRC and master clocked on the same (previously physically slaved) I2S channel.

A side note, look at the layout example with the forementioned tristate buffer; You start by connecting pads to all gate pins of the IC, then you untangle the pads, then you choose which gate goes where and connect, and sometimes they detangle all the way like IC6 8)

[Kjetil]

EDIT: Preliminary layout deleted, still some minor adjustments to make :eating:

[5th element]

You look like you're making a lot of really nice progress on that. Personally I used an Abracon ABLNO oscillator for the high quality reference to the ES9018. These are expensive. The DAC sounds amazing though, was it worth it? I don't know but I don't regret the purchase.

[Kjetil]

You look like you're making a lot of really nice progress on that. Personally I used an Abracon ABLNO oscillator for the high quality reference to the ES9018. These are expensive. The DAC sounds amazing though, was it worth it? I don't know but I don't regret the purchase.

Nice specs on that one too, but it lacks an enable input. Although both oscillators could run side by side, I feel much better turning the unused oscillator in standby (whether it be the shared LDO regulator and noise concerns, or simply just current consumption). Also, I didn't lookup the cost, but the 40EUR for two Crystek oscillators is really more than enough dough, as I am thinking I might make a small batch of these, and would probably have to give some away for free to anyone capable and willing to aid in Linux development :W The phase noise numbers look quite comparable between the two.

I came to the realization I had more than enough space on top layer for even oscillators if I only compressed the EEPROM packages and moved the 1.8V regulator a bit, so I did a makeover. I really like single side component boards due to the low-tech manufacturing requirements (and cost). Now I have one clock bank in single ended LVCMOS feeding DSP, BeagleBone and I2S header at Fosc/2, while the other bank exports two LVDS/LVPECL clocks at flexible clock divisor to pads for twisted pair wires. Just add a LVDS/LVPECL receiver on baseboard and terminate according to chosen format, should improve clock distribution on complex baseboards.

Still a couple of loose ends to tie up, but I'm closing in on it :T

[JonMarsh]

Matt, there's one thing I've consistently heard from people working with the Sabre DAC chips, including the guys at AURALiC; they are quite sensitive to the quality of clocks, and the quality of voltage regulation and noise on the power. They had nine different versions of the prototype in evaluation before settling on their final configuration, with many power supply revisions to improve the effective bit resolution. Their comment about the ES9018 data sheet was that it was an error riddled nightmare with a lot of vital information missing- I.E., figure it out for yourself on the bench, I guess. You should note they bypassed the up sampling mode of the ES9018 most of the time and implemented their own solution- though in some cases it works in tandem with the internal one.

They also switched to the TI OPA1612 for the I/V buffer and output filter/driver, because the LM4562, quiet and low distortion as it is, was compromising the performance of the DAC chip. For reference, the OPA1612 is rated at 1.1nV /root Hz input noise. That part is also available in a single, the OPA1611; some different package options, including thermal pad for the chip for cooling- it's a near rail-rail opamp, and capable of pretty high output current. ~27V/us slow rate. Low, VERY low distortion.

opa1612.pdf

I'm looking at this part (expensive, by the way!) for the instrumentation style front end buffer for my Class D project, and also for a possible DIY preamp buffer for simple setups using the single ended driven differential configuration (used in Pro gear, and also the Mola Preamp). I'm pondering ripping apart my passive preamp with Shallco attenuator to manage the gain control aspect.



It sounds to me like they put a LOT of effort in to optimizing the end result. I still haven't had the time to set it up properly and do listening tests against the TotalDAC-D1 Dual that I own- it's a combination of how my working day is scheduled, working 7 days a week since June *(got the Vega in early July) and GF has her special shows to watch in the family room in the evening, so I can't do audio then even if I was up and awake for it- which after 9, I'm not (usually getting up between 4 and 4:30 AM)

I do have a Mutec to pair with it as well as another LPFRS rubidium oscillator and low noise analog supply- maybe after this training and current marathon are done. Unfortunately, I know there's another marathon waiting in the wings, but don't know if my boss has gotten approval of it by the div. VP. that would run through April.

Another colleague of mine and I have gotten quite fond of low noise wide bandwidth shunt regulators- he's bought a lot of the Paul Hynes ones, but apparently Paul's health has taken a turn for the worse, and there probably won't be any more of them produced.

[Kjetil]

Jon, Matt, if I may ask, what would your recommendation for regulator topology be for my oscillator supply? They are 3.3V LVCMOS oscillators operating just above 40MHz, they draw 15mA typ / 25mA max and the one not being used will stay in shutdown mode. As of now, I have a TPS79433 LDO in the position.

[JonMarsh]

That TI part looks fine to me; looks like a very low noise figure. I'm looking at some similar adjustable range regulators from them, the TPS7A30 and TPS7A49. For your application, to keep the output impedance low, I'd consider loading them with a current source to get the output impedance a bit lower (old audio trick); it doesn't turn them into a shunt regulator, but if you are seeing anything other than a steady current draw on the output, you'll usually have better load step response going from, say, 45 mA down to 25mA than from 25mA to zero. Of course, that depends on thermals, but you're way over rated for the loads you say you plan, even with 5V input. COG ceramics? i don't like the capacitance variation with voltage of the other types.

[Kjetil]

That TI part looks fine to me; looks like a very low noise figure. I'm looking at some similar adjustable range regulators from them, the TPS7A30 and TPS7A49. For your application, to keep the output impedance low, I'd consider loading them with a current source to get the output impedance a bit lower (old audio trick); it doesn't turn them into a shunt regulator, but if you are seeing anything other than a steady current draw on the output, you'll usually have better load step response going from, say, 45 mA down to 25mA than from 25mA to zero. Of course, that depends on thermals, but you're way over rated for the loads you say you plan, even with 5V input. COG ceramics? i don't like the capacitance variation with voltage of the other types.

I'll look into CS loading. C0G ceramics? Are you talking about the local decoupling at the oscillators or the output capacitance for the LDO? 100nF C0G doesn't seem to come any smaller than 1206 pkg 8O

BTW, found an impressively specced LT LDO, LT3042, 0.8uVRMS 10Hz-100kHz and 79dB PSRR at 1MHz, but the transient response (page 11) is not on par, unfortunately.

[5th element]

The forums were down yesterday so I couldn't post this but here we go.

I'd use an LT3042 for the oscillator supplies. If this chip had been out when I built my boards up I would have also used it. Ridiculous performance for an integrated regulator solution. Since I wrote this you had found that regulator yourself. I wouldn't worry too much about its transient performance. At high frequencies the low impedance, transient power requirements are provided by the local decoupling rather than the supply itself. From what I have gathered over the years low noise is usually of primary importance for low jitter clocks, with some designs going so far as to use extensive post regulator CLC filtering. This would obviously destroy the specific regulators ability to deliver current on demand, but helps to keep the supplies very low noise.

I hear you Jon about the sensitivity of the power supplies. I didn't to skimp out here either. I went for TIs LP5907. A separate regulator for each power supply pin with a nice low ESR polymer lytic per supply pin too.

I chose to use the ADA4898 for I/V conversion, and am using AD8610s that I had on hand for the differential stage following it. Some tech savvy member of DIYaudio recommended them speaking highly of their linearised input stage topology.

Yes the ESS datasheet is rather lacking but I have extensive experience with DACs so what was necessary to be inferred was inferred and everything turned out decently.

Kjetil my PCB for the ADAU is actually only two layer, I only have the ability to make two layer boards myself as I don't use fabrication facilities. It works great. Yes I had to be quite careful with the layout but I managed to fit everything in whilst leaving the ground plane intact.

[Kjetil]

Thanks Matt, I'll try the LT3042 then :T The layout started to get pretty packed with the big oscillator pair so I decided to move down in package size to the CCHD-575, very close in performance and much smaller (5 x 7.5mm). I did a quick layout with the LT3042, I don't have experience with this type of low noise layout, but I put the power and ground connection at the LDO only, and routed on top layer from there. I turned off thermals on the planes to keep things compact, but kept the planes small enough so hand soldering probably won't be a problem with a bit of heat. My very preliminary plan is a 0805 4.7uF X5R/X7R in input and output, and I've placed a 1206 pad for 100nF C0G/NP0 right by the oscillator. Any comments/critique to the layout/configuration would be most welcome.

Kjetil my PCB for the ADAU is actually only two layer, I only have the ability to make two layer boards myself as I don't use fabrication facilities. It works great. Yes I had to be quite careful with the layout but I managed to fit everything in whilst leaving the ground plane intact.

I don't make my own boards, and since 4-layer, 6mil trace/space and 15mil holes have become quite reasonably priced the last years, I usually don't think twice before deciding on 4 layers for sensitive/complex circuits, unless the project is very cost sensitive and requiring a large PCB. I remember just 5-6 years ago, when I was still in college, the price was quite different for the same technology.

[ergo]

I'm looking at this part (expensive, by the way!) for the instrumentation style front end buffer for my Class D project, and also for a possible DIY preamp buffer for simple setups using the single ended driven differential configuration (used in Pro gear, and also the Mola Preamp). I'm pondering ripping apart my passive preamp with Shallco attenuator to manage the gain control aspect.

There is a thread going over at DIYaudio about Bruno Butzey's preamp published in Linear audio book and also accessible here that uses somewhat similar concept.

http://www.hypex.nl/docs/papers/The%20G%20Word.pdf

I have a PCB for this that I got with the book and making a BOM for it with a plan to build one (and for now put in front of Icepower modules)

[Kjetil]

I guess my question is really not so much the layout part but the bulk capacitance. I could instead go with a 100nF X5R at the regulator, followed by a ~150uF low-ESR SVPE OS-CON, and then a 100nF C0G/NP0 at the oscillator.

[5th element]

Usually speaking, with high frequency digital circuits, the data sheets outline the exact decoupling and bulk decoupling requirements for proper operation. The same goes for the regulators needs with respect to stability.

For high performance parts, such as the LT3042, additional details are usually given with regards to how the performance is changed/improved if you have the space and/or the budget to use larger capacitors.

There is usually no point in adding in more capacitance than is required and is some cases it can actually degrade the performance is lead to some regulators becoming unstable.

[Kjetil]

OK, DSP design phase seem to be nearing completion. :^x

Whether the source is asynchronously resampled from SPDIF or synchronously clocked audio from BeagleBone, the I2S signals will be synchronous to the oscillator. I'm contemplating the DAC board now (an important aspect to have in mind before finalizing the DSP design), and my immediate thoughts are;

I grab the I2S DATA (several lines) and LRCLK/BCLK from the I2S header, feeding them into flip-flops near the DACs for reclocking (I don't know if this is needed if the MCLK itself is low jitter). Then, I take one of the differential LVDS/LVPECL clock lines from the DSP board (straight from the Si53311 buffer), and feed it to a similar clock buffer on the DAC board (these buffers typically add <50fs jitter). This second clock buffer will fan out clocks for reclocking flip-flops and for DAC MCLKs. DACs will probably be PCM1792A/PCM1794A, WM8741, AD1955 or similar...

[5th element]

I don't think you will need to use any flip flops for re-clocking providing you keep the wires short between boards. In fact I'm not sure if re-clocking would be preferable anyway, even if you use longer connections simply buffering and terminating the lines should be more than adequate. Still you need to use pretty long wires/traces before proper termination is necessary with I2S lines. Sure always use a 47R resistor in series with the lines at the source, but besides that you're usually okay.

[Kjetil]

Not sure about the reclocking part :scratchhead: it'll be on the baseboard side regardless and a quad D-type FF per DAC would do. It's probably a buck or two to clean up all I2S lines by MCLK, unless I'd introduce some unexpected negative side effects with it...?

I read a bunch of posts at some other forum by a really helpful and polite guy called Jocko Homo :rant: He's a strong advocate for low phase noise well below where most vendors specify their parts, I'd probably take his 0.1Hz PN point of views with a pinch of salt but I've been looking around for a solution with decent PN specs down to 1Hz. Word on the street is there are some competitively priced XOs with pretty good cut originating from Japan, NZ2520SD. I haven't gotten around to reading all documentation yet, nor sorted out availability issues, but that's about where I'm at. Phase noise is way better than Crystek. Small too :T I am under no circumstances going to drop the $$$$ needed to get two high quality (eg Wenzel/Morion/Vectron) OCXOs custom cut for audio frequencies, nor do I have the equipment to sort through piles of crystals to build a discrete low-jitter solution. I don't even want to get into the Kwak clock designs, simply looking for the best specs I can get in an integrated crystal oscillator, at a maximum two digit price point.

On the DAC side, would it make any sense at all with a 96kHz device, or would I be wize to choose a 192kHz one? Any caveeats? I'm drooling a bit on a very expensive fairly old device from TI, the PCM1704 R-2R DAC. Production status is NRND, but that doesn't really bother me on the baseboard side, it'll never be more than a one-off board anyway.

[Kjetil]

It appears I might have access to some phase noise measurement capable gadgets after all, so I'm the process of redesigning the clocks. Since I'm going to get a few made of these, I can get crystals from Laptech by custom order (they have a 5pcs per freq minimum order I think). Odds are I'll use the HC-37/U or HC-35/U package. AT cut, fundamental frequencies, high unloaded Q. Oscillator topology will be a simple Pierce oscillator (more theory). The optimal choice for the inverting amplifier would probably be JFETs but for simplicity I'll use single unbuffered LVC inverters instead, at least to start with. Two inverter stages with the oscillators inverting amplifier producing something like a sinewave, and the second inverter (output amplifier) to square things up. Furthermore, I'm thinking I'll replace the clock buffer with a simpler one without divider, and that can operate at 1.5V-2.5V for clock levels with level shifting to 3.3V outputs, so that I can keep the oscillators at low voltage, reducing risk of overdriving the crystals.

None of the clock multiplexers/buffers seem to specify added jitter at low frequencies, but I don't think this is a problem. I think (not completely sure yet though) they only increase the noise floor a bit, at the >1kHz frequencies where phase noise is at incredibly low levels anyway, and that they won't compromise the close-in phase noise (say below 100Hz) by much.

[Kjetil]

This layout certainly took a bit longer than expected, but I guess I should expect steep learning curves when diving head first into audio electronics. As mentioned, the oscillators has been made discrete Pierce; an inverting amplifier (180deg phase shift) into an RC filter [Rlim,C2] to throw away the gain with 90deg phase shift, driving (and not overdriving) the crystal into the load capacitor C1 (load capacitance seen is 1/(1/C2+1/(C1+Cgate+Cmiller)) or put simpler; C2 in series with (C1+Cgate+Cmiller), usual target is 20-22pF given by crystal specs) adding another 90deg phase shift, and back into the inverting amp completing the oscillator feedback loop. Simple in theory, but it will take some effort finding optimal Rlim to get the drive level right for best performance with the crystals I get.

Due to the sheer number of low-noise regulators (6 of them now not counting DSP regs, all with filtered inputs) I used ADP150 for their good performance in itty bitty package size. A single MCLK coax is available through 50ohm MMCX, and SPDIF now inputs to a 75ohm MCX connector, into a pulse transformer, impedance matched and buffered. BCLK/FCLK from BeagleBone each feeds a single LVCMOS buffer into a triple LVCMOS buffer (one set to DSP input domain, one set to output domain, and one set exported to baseboard), source terminated into the loads. Source termination is also used on all clock lines and on BCLK/FCLK/DATAOUT I2S lines from the SigmaDSP. I got rid of the optic/SPDIF output stage (no space for it any more), that signal is now available to baseboard.

The revised layout seems pretty much finished, and I don't expect to make any big changes from this point forward. Still some delay before ordering boards though, to check, double check, and triple check everything.

Yeah, and there is no QFN packages left on board (I hate to hand solder those, even with hot air), so the boards can actually be soldered by hand and iron (that is if you manage 0402 SMDs, 0.5mm pitch ICs and EPADs, not that difficult with some technique and a good terminal) 8)

Actually, despite all the back and forth in the design process, the progress isn't that bad given where I started at the beginning of this thread just over a month ago Nevertheless, I think this it for this thread. I've wandered so far off the original topic the mods should probably have slapped me in my face, I'll return in the digital forum when I have something to report. :later: